Digital hardware architectures of Kohonen's self organizing feature maps with exponential neighboring function

Jorge Peña; Mauricio Vanegas; Andrés Valencia

doi:10.1109/RECONF.2006.307761

Digital hardware architectures of Kohonen's self organizing feature maps with exponential neighboring function

Jorge Peña
, Mauricio Vanegas
, Andrés Valencia

Design Studies

Research output: Chapter in Book/Conference proceeding › Conference and proceedings › peer-review

26 Scopus citations

Abstract

Kohonen maps are self-organizing neural networks that categorize input data, capturing its topology and probability distribution. Efficient hardware implementations of such maps require the definition of a certain number of simplifications to the original algorithm. In particular, multiplications have to be avoided by means of choices in the distance metric, the neighborhood function and the set of learning parameter values. In this paper, one-dimensional and bi-dimensional Kohonen maps with exponential neighboring function and Cityblock and Chessboard norms are defined, and their hardware architecture is presented. VHDL simulations and synthesis on an FPGA of the proposed architectures demonstrate both satisfactory functionality and feasibility.

Original language	English
Title of host publication	Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006
Pages	114-121
Number of pages	8
DOIs	https://doi.org/10.1109/RECONF.2006.307761
State	Published - 2006
Event	2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006 - San Luis Potosi, Mexico Duration: 20 Sep 2006 → 22 Sep 2006

Publication series

Name	Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006

Conference

Conference	2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006
Country/Territory	Mexico
City	San Luis Potosi
Period	20/09/06 → 22/09/06

Access to Document

10.1109/RECONF.2006.307761

Cite this

Peña, J., Vanegas, M., & Valencia, A. (2006). Digital hardware architectures of Kohonen's self organizing feature maps with exponential neighboring function. In Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006 (pp. 114-121). Article 4099981 (Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006). https://doi.org/10.1109/RECONF.2006.307761

Peña, Jorge ; Vanegas, Mauricio ; Valencia, Andrés. / Digital hardware architectures of Kohonen's self organizing feature maps with exponential neighboring function. Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006. 2006. pp. 114-121 (Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006).

@inproceedings{03ee7ce81b064f86a259669e9f7ae808,

title = "Digital hardware architectures of Kohonen's self organizing feature maps with exponential neighboring function",

abstract = "Kohonen maps are self-organizing neural networks that categorize input data, capturing its topology and probability distribution. Efficient hardware implementations of such maps require the definition of a certain number of simplifications to the original algorithm. In particular, multiplications have to be avoided by means of choices in the distance metric, the neighborhood function and the set of learning parameter values. In this paper, one-dimensional and bi-dimensional Kohonen maps with exponential neighboring function and Cityblock and Chessboard norms are defined, and their hardware architecture is presented. VHDL simulations and synthesis on an FPGA of the proposed architectures demonstrate both satisfactory functionality and feasibility.",

author = "Jorge Pe{\~n}a and Mauricio Vanegas and Andr{\'e}s Valencia",

year = "2006",

doi = "10.1109/RECONF.2006.307761",

language = "Ingl{\'e}s",

isbn = "1424406900",

series = "Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006",

pages = "114--121",

booktitle = "Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006",

note = "2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006 ; Conference date: 20-09-2006 Through 22-09-2006",

}

Peña, J, Vanegas, M & Valencia, A 2006, Digital hardware architectures of Kohonen's self organizing feature maps with exponential neighboring function. in Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006., 4099981, Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006, pp. 114-121, 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006, San Luis Potosi, Mexico, 20/09/06. https://doi.org/10.1109/RECONF.2006.307761

Digital hardware architectures of Kohonen's self organizing feature maps with exponential neighboring function. / Peña, Jorge; Vanegas, Mauricio; Valencia, Andrés.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006. 2006. p. 114-121 4099981 (Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006).

Research output: Chapter in Book/Conference proceeding › Conference and proceedings › peer-review

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N2 - Kohonen maps are self-organizing neural networks that categorize input data, capturing its topology and probability distribution. Efficient hardware implementations of such maps require the definition of a certain number of simplifications to the original algorithm. In particular, multiplications have to be avoided by means of choices in the distance metric, the neighborhood function and the set of learning parameter values. In this paper, one-dimensional and bi-dimensional Kohonen maps with exponential neighboring function and Cityblock and Chessboard norms are defined, and their hardware architecture is presented. VHDL simulations and synthesis on an FPGA of the proposed architectures demonstrate both satisfactory functionality and feasibility.

AB - Kohonen maps are self-organizing neural networks that categorize input data, capturing its topology and probability distribution. Efficient hardware implementations of such maps require the definition of a certain number of simplifications to the original algorithm. In particular, multiplications have to be avoided by means of choices in the distance metric, the neighborhood function and the set of learning parameter values. In this paper, one-dimensional and bi-dimensional Kohonen maps with exponential neighboring function and Cityblock and Chessboard norms are defined, and their hardware architecture is presented. VHDL simulations and synthesis on an FPGA of the proposed architectures demonstrate both satisfactory functionality and feasibility.

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M3 - Ponencia publicada en las memorias del evento con ISBN

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SN - 1424406900

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BT - Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006

T2 - 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006

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Peña J, Vanegas M, Valencia A. Digital hardware architectures of Kohonen's self organizing feature maps with exponential neighboring function. In Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006. 2006. p. 114-121. 4099981. (Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006). doi: 10.1109/RECONF.2006.307761

Digital hardware architectures of Kohonen's self organizing feature maps with exponential neighboring function

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