Digital hardware architectures of Kohonen's self organizing feature maps with exponential neighboring function

Kohonen maps are self-organizing neural networks that categorize input data, capturing its topology and probability distribution. Efficient hardware implementations of such maps require the definition of a certain number of simplifications to the original algorithm. In particular, multiplications have to be avoided by means of choices in the distance metric, the neighborhood function and the set of learning parameter values. In this paper, one-dimensional and bi-dimensional Kohonen maps with exponential neighboring function and Cityblock and Chessboard norms are defined, and their hardware architecture is presented. VHDL simulations and synthesis on an FPGA of the proposed architectures demonstrate both satisfactory functionality and feasibility.